The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2014
Filed:
Aug. 17, 2011
Satish Sathe, San Ramon, CA (US);
Perrine Peresse, Tourrettes sur Loup, FR;
Anjan Rudra, Maharashtra, IN;
Keyur Chudgar, San Jose, CA (US);
Satish Sathe, San Ramon, CA (US);
Perrine Peresse, Tourrettes sur Loup, FR;
Anjan Rudra, Maharashtra, IN;
Keyur Chudgar, San Jose, CA (US);
Applied Micro Circuits Corporation, Sunnyvale, CA (US);
Abstract
In a system-on-chip (SoC), a method is provided for partitioning access to resources. A plurality of processors is provided, including a configuration master (CM) processor, a memory, a plurality of OSs, and accessible resources. The method creates a mapping table with a plurality of entries, each entry cross-referencing a range of destination addresses with a domain ID, where each domain ID is associated with a corresponding processor. Access requests to the resource are accepted from the plurality of processors. Each access request includes a domain ID and a destination address. A mapping table is consulted to determine the range of destination addresses associated with the access request domain IDs. The accesses are authorized in response to the access request destination addresses matching the range of destination addresses in the mapping table, and the authorized access requests are sent to the destination addresses of the requested resources.