The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2014

Filed:

Dec. 04, 2006
Applicants:

Yoichi Nishida, Kanagawa, JP;

Takayuki Ejima, Fukuoka, JP;

Akihiro Miyazaki, Osaka, JP;

Yasunori Sato, Osaka, JP;

Inventors:

Yoichi Nishida, Kanagawa, JP;

Takayuki Ejima, Fukuoka, JP;

Akihiro Miyazaki, Osaka, JP;

Yasunori Sato, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G11B 19/02 (2006.01); G11B 20/10 (2006.01); H04N 9/877 (2006.01); H04N 19/44 (2014.01); H04N 5/781 (2006.01); H04N 9/804 (2006.01); H04N 5/907 (2006.01); H04N 5/85 (2006.01);
U.S. Cl.
CPC ...
G11B 20/10 (2013.01); H04N 5/781 (2013.01); G11B 19/02 (2013.01); H04N 9/8042 (2013.01); G06F 1/3203 (2013.01); H04N 9/8047 (2013.01); Y02B 60/1217 (2013.01); Y02B 60/32 (2013.01); G06F 1/324 (2013.01); H04N 9/877 (2013.01); H04N 5/907 (2013.01); H04N 5/85 (2013.01); H04N 19/00533 (2013.01);
Abstract

A data processor comprises a decoder for decoding the compressed data into decoded data while reading the compressed data from a first data storage, a second data storage for storing therein the decoded data, a DA converter for converting the decoded data into an analog signal while reading the decoded data in real-time, a first controller for controlling the decoder to perform intermittent operation by executing a process between reading the compressed data and storing the decoded data at a speed faster than real-time, a clock/power controller for making a restriction of power consumption of the decoder and the first controller in downtime of the intermittent operation, a second controller for outputting a control signal in accordance with the storage state of the decoded data, and an activation controller for controlling the clock/power controller to lift the restriction in response to reception of the control signal.


Find Patent Forward Citations

Loading…