The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2014
Filed:
Jun. 10, 2010
Yosef Kreinin, Jerusalem, IL;
Gil Dogon, Jerusalem, IL;
Emmanuel Sixsou, Jerusalem, IL;
Yosi Arbeli, Jerusalem, IL;
Mois Navon, Efrat, IL;
Roman Sajman, Givat Zeev, IL;
Yosef Kreinin, Jerusalem, IL;
Gil Dogon, Jerusalem, IL;
Emmanuel Sixsou, Jerusalem, IL;
Yosi Arbeli, Jerusalem, IL;
Mois Navon, Efrat, IL;
Roman Sajman, Givat Zeev, IL;
Mobileye Technologies Limited, Nicosia, CY;
Abstract
An image processing system including a vector processor and a memory adapted for attaching to the vector processor. The memory is adapted to store multiple image frames. The vector processor includes an address generator operatively attached to the memory to access the memory. The address generator is adapted for calculating addresses of the memory over the multiple image frames. The addresses may be calculated over the image frames based upon an image parameter. The image parameter may specify which of the image frames are processed simultaneously. A scalar processor may be attached to the vector processor. The scalar processor provides the image parameter(s) to the address generator for address calculation over the multiple image frames. An input register may be attached to the vector processor. The input register may be adapted to receive a very long instruction word (VLIW) instruction. The VLIW instruction may be configured to transfer only: (i) parameters for image processing calculations over the image frames by the ALU units and (ii) a single bit to the address generator.