The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2014

Filed:

May. 03, 2012
Applicants:

Lin Han, San Jose, CA (US);

Renwei LI, Fremont, CA (US);

Xiaoqian Wu, Beijing, CN;

Shujin Zhang, Palo Alto, CA (US);

Katherine Zhao, San Jose, CA (US);

Inventors:

Lin Han, San Jose, CA (US);

Renwei Li, Fremont, CA (US);

Xiaoqian Wu, Beijing, CN;

Shujin Zhang, Palo Alto, CA (US);

Katherine Zhao, San Jose, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/28 (2006.01); H04L 12/775 (2013.01); H04L 12/721 (2013.01);
U.S. Cl.
CPC ...
H04L 45/58 (2013.01); H04L 45/66 (2013.01);
Abstract

One embodiment of the present invention provides a computing system. The computing system includes a processor, a memory, a logical switch management mechanism, and a layer-2 path management mechanism. The logical switch management mechanism operates the computing system in conjunction with a plurality of remote switches as a single logical switch. The layer-2 path management mechanism includes a path calculation mechanism and a layer-2 forwarding table. The path calculation mechanism calculates layer-2 shortest paths among the computing system and the remote switches. The layer-2 forwarding table is for a first switch in the plurality of remote switches and created based on one or more of the shortest paths, wherein a respective entry in the forwarding table corresponds to a layer-2 network address. The layer-2 path management mechanism suppresses advertisement of the shortest paths outside of the logical switch, thereby hiding internal paths of the logical switch.


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