The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2014

Filed:

Nov. 08, 2010
Applicants:

Norifumi Kameshiro, Tokyo, JP;

Haruka Shimizu, Kodaira, JP;

Inventors:

Norifumi Kameshiro, Tokyo, JP;

Haruka Shimizu, Kodaira, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/808 (2006.01); H01L 29/06 (2006.01); H01L 29/861 (2006.01); H01L 29/872 (2006.01); H01L 29/12 (2006.01); H01L 29/66 (2006.01); H01L 29/16 (2006.01); H01L 29/10 (2006.01); H01L 29/80 (2006.01); H01L 29/47 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1608 (2013.01); H01L 29/7811 (2013.01); H01L 29/0878 (2013.01); H01L 29/808 (2013.01); H01L 29/0615 (2013.01); H01L 29/861 (2013.01); H01L 29/872 (2013.01); H01L 29/06 (2013.01); H01L 29/12 (2013.01); H01L 29/78 (2013.01); H01L 29/0843 (2013.01); H01L 29/6606 (2013.01); H01L 29/1095 (2013.01); H01L 29/80 (2013.01); H01L 29/0692 (2013.01); H01L 29/8083 (2013.01); H01L 29/47 (2013.01);
Abstract

On a front surface of a region where a junction termination extension structure of a semiconductor device using silicon carbide is formed, a structure having an n-type semiconductor region with a concentration relatively higher than a concentration of an n-type drift layer is formed. An edge of the junction termination extension structure located on a side away from an active region is surrounded from its bottom surface to its front surface by an n-type semiconductor region. By this means, it is possible to provide a device with a low resistance while ensuring a withstand voltage, or by decreasing the resistance of the device, it is possible to provide a device with low power loss.


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