The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2014

Filed:

Aug. 16, 2012
Applicants:

Seung-hee Nam, Gyeonggi-do, KR;

Soon-sung Yoo, Gyeonggi-do, KR;

Tae-hyoung Moon, Gyeonggi-do, KR;

Tae-joon Song, Gyeonggi-do, KR;

Kyu-hwang Lee, Seoul, KR;

Inventors:

Seung-Hee Nam, Gyeonggi-do, KR;

Soon-Sung Yoo, Gyeonggi-do, KR;

Tae-Hyoung Moon, Gyeonggi-do, KR;

Tae-Joon Song, Gyeonggi-do, KR;

Kyu-Hwang Lee, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/14 (2006.01); H01L 27/12 (2006.01); H01L 27/32 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1214 (2013.01); H01L 27/1259 (2013.01); H01L 27/124 (2013.01); H01L 27/1288 (2013.01); H01L 27/3279 (2013.01);
Abstract

An array substrate for a display device and manufacturing method thereof is disclosed. The device comprises: a substrate; a gate line formed on the substrate along a first direction; a data line formed over the substrate along a second direction, wherein the data line and the gate line cross each other to define a pixel region; a thin film transistor formed in the pixel region, and having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode; a pixel electrode formed in the pixel region and connected to the drain electrode; a first auxiliary gate pattern formed over the gate line and contacting the gate line; and a first auxiliary data pattern formed over the data line and contacting the data line.


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