The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 18, 2014
Filed:
Mar. 28, 2008
Applicant:
Lars-erik Wernersson, Lund, SE;
Inventor:
Lars-Erik Wernersson, Lund, SE;
Assignee:
Qunano AB, Lund, SE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 51/56 (2006.01); H01L 29/06 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01); H01L 27/092 (2006.01); B82Y 10/00 (2011.01); H01L 21/8234 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78642 (2013.01); H01L 29/0676 (2013.01); H01L 29/78687 (2013.01); H01L 21/823885 (2013.01); H01L 27/088 (2013.01); H01L 29/78684 (2013.01); H01L 27/092 (2013.01); B82Y 10/00 (2013.01); H01L 29/78681 (2013.01); H01L 29/0673 (2013.01); H01L 21/823487 (2013.01);
Abstract
A nanowire circuit architecture is presented. The technology comprises of nanowire transistors (), and optionally nanowire capacitors () and nanowire resistors (), that are integrated using two levels of interconnects only (). Implementations of ring-oscillators, sample-and-hold circuits, and comparators may be realized in this nanowire circuit architecture. Circuit input and circuit output as well as the transistor connections within each circuit are provided in the two levels of interconnects ().