The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 18, 2014

Filed:

Dec. 12, 2013
Applicant:

Panasonic Corporation, Osaka, JP;

Inventor:

Kenji Yoneda, Kyoto, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/265 (2006.01); H01L 21/687 (2006.01); H01L 29/66 (2006.01); H01L 29/04 (2006.01);
U.S. Cl.
CPC ...
H01L 21/26513 (2013.01); H01J 2237/24528 (2013.01); H01L 21/26586 (2013.01); H01L 21/68771 (2013.01); H01L 29/6659 (2013.01); H01L 21/68764 (2013.01); H01L 29/045 (2013.01); H01J 2237/20207 (2013.01); H01J 2237/31701 (2013.01); H01L 29/6656 (2013.01);
Abstract

Provided is a method for manufacturing a semiconductor device which includes, on a wafer which has a notch, a plurality of transistors parallel with and perpendicular to a notch direction extending between the center of the wafer and the notch, the method including: preparing the wafer having the front surface which has Off angle of at least 2 degrees and at most 2.8 degrees from plane in a direction in which Twist angle relative to the notch direction is at least 12.5 degrees and at most 32.5 degrees; and doping impurities into the front surface of the wafer in a direction perpendicular to the front surface.


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