The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2014

Filed:

Apr. 25, 2008
Applicants:

Seiji Miura, Tokyo, JP;

Yoshinori Haraguchi, Tokyo, JP;

Kazuhiko Abe, Tokyo, JP;

Shoji Kaneko, Tokyo, JP;

Inventors:

Seiji Miura, Tokyo, JP;

Yoshinori Haraguchi, Tokyo, JP;

Kazuhiko Abe, Tokyo, JP;

Shoji Kaneko, Tokyo, JP;

Assignee:

PS4 Luxco S.a.r.l., Luxembourg, LU;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G11C 7/00 (2006.01); G06F 13/42 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4243 (2013.01);
Abstract

The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the volatile memory, and the nonvolatile memory and reducing the number of connection signals, processing speed is increased while maintaining the scalability of memory capacity. When transferring data of the nonvolatile memory to the volatile memory, error correction is performed, thereby improving reliability. The information processing system including the plurality of chips is configured as an information-processing system module in which the chips are alternately stacked and arranged, and wired by a ball grid array (BGA) or by bonding between the chips.


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