The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2014
Filed:
May. 24, 2011
Brian E. Bakke, Rochester, MN (US);
Brian L. Bowles, Rochester, MN (US);
Michael J. Carnevale, Rochester, MN (US);
Robert E. Galbraith, Rochester, MN (US);
Adrian C. Gerhard, Rochester, MN (US);
Murali N. Iyer, Rochester, MN (US);
Daniel F. Moertl, Rochester, MN (US);
Mark J. Moran, Minneapolis, MN (US);
Gowrisankar Radhakrishnan, Rochester, MN (US);
Rick A. Weckwerth, Oronoco, MN (US);
Donald J. Ziebarth, Rochester, MN (US);
Brian E. Bakke, Rochester, MN (US);
Brian L. Bowles, Rochester, MN (US);
Michael J. Carnevale, Rochester, MN (US);
Robert E. Galbraith, Rochester, MN (US);
Adrian C. Gerhard, Rochester, MN (US);
Murali N. Iyer, Rochester, MN (US);
Daniel F. Moertl, Rochester, MN (US);
Mark J. Moran, Minneapolis, MN (US);
Gowrisankar Radhakrishnan, Rochester, MN (US);
Rick A. Weckwerth, Oronoco, MN (US);
Donald J. Ziebarth, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and controller for implementing storage adapter performance optimization with parity update footprint mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. Each of a first controller and a second controller includes a plurality of hardware engines, a control store configured to store parity update footprint (PUFP) data; a data store; and a nonvolatile random access memory (NVRAM). One controller operates in a first initiator mode for transferring PUFP data to the other controller operating in a target mode. Respective initiator hardware engines transfers PUFP data from the initiator control store, selectively updating PUFP data, and writing PUFP data to the initiator data store and to the initiator NVRAM, and simultaneously transmitting PUFP data to the other controller. Respective target hardware engines write PUFP data to the target data store and the target NVRAM, eliminating firmware operations.