The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2014

Filed:

Feb. 21, 2011
Applicant:

Tomochika Takeshima, Hamamatsu, JP;

Inventor:

Tomochika Takeshima, Hamamatsu, JP;

Assignee:

Hamamatsu Photonics K.K., Hamamatsu-shi, Shizuoka, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/00 (2006.01); G06T 7/20 (2006.01); G01N 25/72 (2006.01); G06T 7/00 (2006.01); G01R 31/311 (2006.01);
U.S. Cl.
CPC ...
G01N 25/72 (2013.01); G06T 7/2033 (2013.01); G06T 2207/20021 (2013.01); G06T 2207/10048 (2013.01); G06T 2207/30148 (2013.01); G06T 7/0004 (2013.01); G06T 2207/20224 (2013.01); G06T 2207/10016 (2013.01); G01R 31/311 (2013.01); G06T 2207/20076 (2013.01);
Abstract

A failure analysis apparatusA is provided with a voltage applying unitfor applying a bias voltage to a semiconductor device S, an imaging devicefor acquiring an image, and an image processing unitfor performing image processing, and the imaging deviceacquires a plurality of analysis images each including a thermal image in a voltage applied state and a plurality of background images in a voltage non-applied state. The image processing unitincludes an imaging position calculating sectionfor calculating an imaging position of each of the analysis images and the background images, an image classifying sectionfor classifying the analysis images and the background images into N image groups based on a region division unit prepared for the imaging position, and a difference image generating sectionfor generating difference images between the analysis images and the background images individually for N image groups. Accordingly, a semiconductor failure analysis apparatus and method capable of suppressing the effect of a shift in imaging position in a thermal analysis image of a semiconductor device can be realized.


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