The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2014

Filed:

Jun. 12, 2013
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Nicolaas Klarinus Johannes Van Winkelhoff, Villard Bonnot, FR;

Pierre Lemarchand, Grenoble, FR;

Bastien Jean Claude Aghetti, Grenoble, FR;

Virgile Javerliac, Grenoble, FR;

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 29/52 (2006.01);
U.S. Cl.
CPC ...
G11C 29/52 (2013.01); G11C 7/00 (2013.01);
Abstract

A memory device including an array of memory cells arranged as a plurality of rows and columns. Write circuitry then controls a voltage level of the associated at least one bit line for each of the addressed memory cells to cause write data to be written into the addressed memory cells. In the presence of an asserted erase signal, a decoder circuitry's operation is modified such that it issues, independently of the clock signal, an asserted word line signal on the word line associated with each row in a predetermined erase region of the array. Further, the write circuitry's operation is modified so that it controls the voltage level of the associated at least one bit line for each memory cell in the predetermined erase region, in order to cause erase write data to be written into the memory cells of the predetermined erase region.


Find Patent Forward Citations

Loading…