The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2014

Filed:

Apr. 09, 2009
Applicants:

Young-wook Lee, Suwon-si, KR;

Hwa-yeul OH, Seoul, KR;

Pil-sang Yun, Seoul, KR;

Je-hyeong Park, Hwaseong-si, KR;

Inventors:

Young-Wook Lee, Suwon-si, KR;

Hwa-Yeul Oh, Seoul, KR;

Pil-Sang Yun, Seoul, KR;

Je-Hyeong Park, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1362 (2006.01); G09G 3/36 (2006.01); G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
G02F 1/136213 (2013.01); G09G 2300/0809 (2013.01); G02F 2001/134345 (2013.01); G09G 2320/028 (2013.01); G09G 3/3659 (2013.01); G09G 2300/0447 (2013.01); G09G 2300/0876 (2013.01); G09G 2300/0443 (2013.01); G02F 1/13624 (2013.01);
Abstract

Embodiments of the present invention relate to a liquid crystal display and a driving method thereof. According to an embodiment, the liquid crystal display comprises a pixel electrode having a first subpixel electrode, a second subpixel electrode, and a third subpixel electrode electrically separated from each other. The liquid crystal display comprises a first thin film transistor connected to the first subpixel electrode, a second thin film transistor connected to the second subpixel electrode, a third thin film transistor connected to the third subpixel electrode, and a fourth thin film transistor connected to the second subpixel electrode and the third subpixel electrode. The liquid crystal display comprises a first gate line connected to the first to third thin film transistors, a second gate line connected to the fourth thin film transistor, a data line connected to the first and second thin film transistors, and a storage electrode line connected to the third thin film transistor.


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