The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2014
Filed:
Dec. 04, 2012
Applicant:
Qualcomm Incorporated, San Diego, CA (US);
Inventors:
Gary John Ballantyne, Christchurch, NZ;
Jeremy D. Dunworth, San Diego, CA (US);
Bhushan Shanti Asuri, San Diego, CA (US);
Assignee:
QUALCOMM Incorporated, San Diego, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01); H03L 7/085 (2006.01); H03L 7/089 (2006.01); H03L 7/093 (2006.01);
U.S. Cl.
CPC ...
H03L 7/085 (2013.01); H03L 7/0891 (2013.01); H03L 7/089 (2013.01); H03L 7/093 (2013.01);
Abstract
A phase locked loop (PLL) device is configurable in an analog phase locked loop and a hybrid analog-digital phase locked loop. In an analog mode, at least a phase detector, an analog loop filter, and a voltage controlled oscillator (VCO), are connected to form an analog loop. In a digital mode, at least the phase detector, the voltage controlled oscillator (VCO), a time to digital converter (TDC), a digital loop filter and a digital to analog converter (DAC) are connected to form the hybrid digital-analog loop.