The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2014
Filed:
Jul. 24, 2009
Applicants:
Adnan A. Siddiquie, Houston, TX (US);
Fangyong Dai, Tomball, TX (US);
Inventors:
Adnan A. Siddiquie, Houston, TX (US);
Fangyong Dai, Tomball, TX (US);
Assignee:
Hewlett-Packard Development Company, L.P., Houston, TX (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/04 (2006.01); G01R 31/12 (2006.01); H01L 23/00 (2006.01); G01R 31/02 (2006.01);
U.S. Cl.
CPC ...
G01R 31/046 (2013.01); H01L 2924/1433 (2013.01); H01L 2924/01079 (2013.01); H01L 2924/01014 (2013.01); H01L 2224/48091 (2013.01); H01L 24/45 (2013.01); H01L 2224/48227 (2013.01); H01L 2924/15311 (2013.01); H01L 2224/45144 (2013.01); G01R 31/026 (2013.01); H01L 2924/14 (2013.01);
Abstract
A system for monitoring a connection to an active pin of an integrated circuit (IC) die, includes an input/output (I/O) cell of an IC die, where the I/O cell is bonded to a bonding pad on a ball grid array (BGA) substrate. The system includes a test point on a printed circuit board (PCB) coupled to the bonding pad which forms an electrical/conductive pathway between the test point and the I/O cell. The system includes a clock waveform injected through a resistor into the test point.