The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2014
Filed:
Dec. 06, 2010
Go Eun Lee, Gyeonggi-do, KR;
Taeje Cho, Yongin-si, KR;
Un-byoung Kang, Hwaseong-si, KR;
Seongmin Ryu, Hwaseong-si, KR;
Jung-hwan Kim, Bucheon-si, KR;
Tae Hong Min, Gumi-si, KR;
Go Eun Lee, Gyeonggi-do, KR;
Taeje Cho, Yongin-si, KR;
Un-Byoung Kang, Hwaseong-si, KR;
Seongmin Ryu, Hwaseong-si, KR;
Jung-Hwan Kim, Bucheon-si, KR;
Tae Hong Min, Gumi-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
A semiconductor apparatus includes a base substrate and a logic chip disposed on the base substrate. The logic chip includes a memory control circuit, a first through silicon via, and a second through silicon via. The memory control circuit is disposed on a first surface of a substrate of the logic chip, and a memory chip is disposed on a second surface of the substrate of the logic chip. The first through silicon via electrically connects the memory control circuit and the memory chip, the second through silicon via is electrically connected to the memory chip and is configured to transmit power for the memory chip, the second through silicon via is electrically insulated from the logic chip, and the first surface of the substrate of the logic chip faces the base substrate.