The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2014
Filed:
Sep. 17, 2009
Applicants:
Satoshi Nakai, Kawasaki, JP;
Masato Suga, Kawasaki, JP;
Jusuke Ogura, Kawasaki, JP;
Inventors:
Assignee:
Fujitsu Semiconductor Limited, Yokohama, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 21/336 (2006.01); H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02225 (2013.01); H01L 21/8238 (2013.01); H01L 21/823807 (2013.01); H01L 29/665 (2013.01); H01L 29/7843 (2013.01);
Abstract
A disclosed semiconductor integrated circuit device includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.