The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2014

Filed:

Jul. 31, 2012
Applicants:

Seokhoon Kim, Hwaseong-si, KR;

Sangsu Kim, Yongin-si, KR;

Chung Geun Koh, Seoul, KR;

Byeongchan Lee, Yongin-si, KR;

Sunghil Lee, Hwaseong-si, KR;

Jinyeong Joe, Suwon-si, KR;

Inventors:

Seokhoon Kim, Hwaseong-si, KR;

Sangsu Kim, Yongin-si, KR;

Chung Geun Koh, Seoul, KR;

Byeongchan Lee, Yongin-si, KR;

Sunghil Lee, Hwaseong-si, KR;

Jinyeong Joe, Suwon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 21/461 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 21/306 (2006.01); H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 29/78 (2006.01); H01L 21/762 (2006.01); H01L 29/165 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 29/165 (2013.01); H01L 29/1037 (2013.01); H01L 29/0847 (2013.01); H01L 21/30608 (2013.01); H01L 29/66545 (2013.01); H01L 21/26586 (2013.01); H01L 29/7834 (2013.01); H01L 29/7835 (2013.01); H01L 21/26593 (2013.01); H01L 21/76237 (2013.01); H01L 21/30604 (2013.01); H01L 21/324 (2013.01); H01L 29/7848 (2013.01); H01L 21/26506 (2013.01); H01L 29/66636 (2013.01); H01L 29/6659 (2013.01); H01L 29/6653 (2013.01); H01L 29/66621 (2013.01);
Abstract

A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.


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