The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2014

Filed:

Mar. 07, 2012
Applicants:

Won-mo Park, Seongnam-si, KR;

Min-wk Hwang, Yongin-si, KR;

Hyun-chul Kim, Seoul, KR;

Inventors:

Won-mo Park, Seongnam-si, KR;

Min-wk Hwang, Yongin-si, KR;

Hyun-chul Kim, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/283 (2006.01); H01L 27/108 (2006.01); G11C 5/04 (2006.01); H01L 21/768 (2006.01); G11C 5/06 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76885 (2013.01); G11C 5/04 (2013.01); H01L 27/10894 (2013.01); H01L 27/10897 (2013.01); G11C 5/06 (2013.01);
Abstract

A method of fabricating a semiconductor memory device includes preparing a semiconductor substrate which is divided into a cell array region and a core and peripheral region adjacent to the cell array region. Signal lines may be formed in a lower layer in a cell region. An insulation layer may be formed on the lower layer. Signal lines connected to cell region signal lines may be formed on an insulation layer of the peripheral region. A capping layer may be formed on the insulation layer and the core and peripheral signal lines. The capping layer may be etched to expose the lower layer of the cell array region and an etch stop may be formed on the lower layer and the core and peripheral region.


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