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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8880855 B1

PDFFull Text
Date of Patent:
Nov. 04, 2014

Filed:

Sep. 15, 2011

Dual register data path architecture with registers in a data file divided into groups and sub-groups

Applicants:

Timothy D Anderson, Dallas, TX (US);

Duc Quang Bui, Grand Prairie, TX (US);

Eric Biscondi, Opio, FR;

Shriram D Moharil, Allen, TX (US);

Mujibur Rahman, Plano, TX (US);

Soujanya Narnur, Dallas, TX (US);

Peter Richard Dent, Irthlingborough, GB;

Ashish Rai Shrivastava, Sugar Land, TX (US);

Inventors:

Timothy D Anderson, Dallas, TX (US);

Duc Quang Bui, Grand Prairie, TX (US);

Eric Biscondi, Opio, FR;

Shriram D Moharil, Allen, TX (US);

Mujibur Rahman, Plano, TX (US);

Soujanya Narnur, Dallas, TX (US);

Peter Richard Dent, Irthlingborough, GB;

Ashish Rai Shrivastava, Sugar Land, TX (US);

Assignee:

Texas Instruments Incorporated, Dallas, TX (US);

Attorneys:

Robert D. Marshall, Jr.

Frederick J. Telecky, Jr.

Primary Examiner:

Andrew Caldwell

Assistant Examiner:

Jyoti Mehta

Int. Cl.
CPC ...
G06F 9/34 (2006.01); H03K 21/00 (2006.01); G06F 1/32 (2006.01); H03K 19/00 (2006.01); G06F 7/483 (2006.01); G06F 12/02 (2006.01); G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3012 (2013.01); H03K 21/00 (2013.01); G06F 1/3296 (2013.01); H03K 19/0016 (2013.01); G06F 7/483 (2013.01); G06F 12/0246 (2013.01);
Abstract

A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.

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