The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2014

Filed:

Sep. 06, 2013
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventor:

Shih-Huang Huang, Hsin-Chu, TW;

Assignee:

MediaTek Inc., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 11/419 (2006.01); G11C 7/12 (2006.01); G11C 11/418 (2006.01); G11C 5/14 (2006.01); G11C 8/08 (2006.01); G11C 7/20 (2006.01);
U.S. Cl.
CPC ...
G11C 7/12 (2013.01); G11C 11/418 (2013.01); G11C 5/148 (2013.01); G11C 2207/2227 (2013.01); G11C 8/08 (2013.01); G11C 7/20 (2013.01);
Abstract

A word line control circuit includes a first PMOS transistor having a gate coupled to a first selection signal; a first NMOS transistor, coupled between a second node and a second voltage terminal, having a gate coupled to an inverted first selection signal, wherein the inverted first selection signal is obtained by inverting the first selection signal; and a plurality of word line drivers, at least one of the word line drivers comprising a first inverter and a second inverter, wherein a positive power terminal of the first inverter is coupled to the first voltage terminal, a negative power terminal of the first inverter is coupled to the second node, a positive power terminal of the second inverter is coupled to the first node, and a negative power terminal of the second inverter is coupled to the second voltage terminal.


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