The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2014

Filed:

Sep. 14, 2012
Applicants:

David Mayhew, Northborough, MA (US);

Mark Hummel, Franklin, MA (US);

Michael Ignatowski, Austin, TX (US);

Inventors:

David Mayhew, Northborough, MA (US);

Mark Hummel, Franklin, MA (US);

Michael Ignatowski, Austin, TX (US);

Assignee:

Advanced Micro Devices, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 13/00 (2006.01); G11C 14/00 (2006.01); H03K 19/00 (2006.01); G11C 11/412 (2006.01); G11C 5/00 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0002 (2013.01); G11C 14/0045 (2013.01); H03K 19/0019 (2013.01); G11C 11/4125 (2013.01); H03K 19/0016 (2013.01); G11C 5/005 (2013.01);
Abstract

A method and apparatus for controlling state information retention determines at least a state information save or restore condition for at least one processing circuit such as one or more CPU or GPU cores or pipelines, in an integrated circuit. In response to determining the state information save or restore condition, the method and apparatus controls either or both of saving or restoring of state information for different virtual machines operating on the processing circuit, into corresponding on-die persistent passive variable resistance memory. The state information save or restore condition is a virtual machine level state information save or restore condition. State information for each of differing virtual machines is saved or restored from differing on-die passive variable resistance memory cells that are assigned on a per-virtual machine basis.


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