The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2014

Filed:

Jul. 08, 2010
Applicants:

Jung-pil Lim, Ulwang-si, KR;

Jae-youl Lee, Yongin-si, KR;

Han-su Pae, Hwaseong-si, KR;

Dong-hoon Baek, Seoul, KR;

Inventors:

Jung-Pil Lim, Ulwang-si, KR;

Jae-Youl Lee, Yongin-si, KR;

Han-Su Pae, Hwaseong-si, KR;

Dong-Hoon Baek, Seoul, KR;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/041 (2006.01); H03L 7/08 (2006.01); H04L 25/02 (2006.01); H03L 7/081 (2006.01); H04L 7/04 (2006.01); H04L 7/08 (2006.01); H04L 7/00 (2006.01); G09G 5/00 (2006.01);
U.S. Cl.
CPC ...
H04L 7/044 (2013.01); H03L 7/0805 (2013.01); H04L 7/046 (2013.01); H04L 25/0272 (2013.01); H04L 7/08 (2013.01); H04L 7/0004 (2013.01); H03L 7/0816 (2013.01); G09G 2310/0275 (2013.01); G09G 5/008 (2013.01);
Abstract

A clock and data recovery (CDR) circuit of a source driver includes a clock recovery unit and a delay locked loop unit. The clock recovery unit receives data bits and a clock code periodically inserted into the data bits through a clock embedded data channel in a display data mode, and is configured to generate a clock signal by detecting an edge of the clock code. The delay locked loop unit is configured to generate a multi-phase clock signal based on the clock signal in the display data mode.


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