Gate shift register and display device using the same

Abstract

A gate shift register and a display device using the same are disclosed. The gate shift register includes a plurality of stages that receive a plurality of gate shift clocks and sequentially output a scan pulse. A k-th stage of the plurality of stages includes a scan direction controller for converting a shift direction of the scan pulse in response to carry signals of previous stages input through first and second input terminals and carry signals of next stages input through third and fourth input terminals, a node controller for controlling charging and discharge operations of each of Q, Q, QB, and QBnodes, a floating prevention unit for applying a low potential voltage to a gate electrode of a discharge TFT based on a voltage of the QBnode or the QBnode, and an output unit for outputting first and second scan pulses.