The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2014

Filed:

Mar. 23, 2012
Applicants:

Albert Ratnakumar, San Jose, CA (US);

Peter Smeys, San Jose, CA (US);

Inventors:

Albert Ratnakumar, San Jose, CA (US);

Peter Smeys, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 21/336 (2006.01); H01L 27/07 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0738 (2013.01); H01L 28/20 (2013.01);
Abstract

Integrated circuits that include resistors are provided. An integrated circuit resistor may include a conductive structure disposed over a semiconductor substrate. An oxide layer may be interposed between the conductive structure and a top surface of the semiconductor substrate. A shallow trench isolation structure may be formed in the substrate directly beneath the oxide layer. The shallow trench isolation structure may be formed in a given region in the substrate that is contained within a surrounding n-well and a deep n-well. The given region within which the shallow trench isolation structure is formed may exhibit native substrate dopant concentration levels; the given region is neither an n-well nor a p-well. The surrounding n-well and the deep n-well may be reversed biased to help fully deplete the given region so that parasitic capacitance levels associated with the resistor are minimized.


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