The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 04, 2014

Filed:

Sep. 27, 2012
Applicant:

Param Corporation, Tokyo, JP;

Inventor:

Hiroshi Yasuda, Hasuda, JP;

Assignee:

Param Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01J 37/147 (2006.01); H01J 37/244 (2006.01); H01J 3/26 (2006.01); G01J 1/42 (2006.01); H01J 37/317 (2006.01); H01J 37/30 (2006.01);
U.S. Cl.
CPC ...
H01J 37/147 (2013.01); H01J 37/3177 (2013.01); H01J 37/3007 (2013.01);
Abstract

A high-accuracy and high-speed lithographic pattern is acquired by forming a square lattice matrix beam group with an interval which is an integral multiple of a beam size in a two-dimensional plane, switching on and off the mesh of a device to be drawn by a bitmap signal, forming a desired beam shape, deflecting the beam to a necessary position, and radiating a beam with a whole blanker being opened after the beam state is stabilized. On and off signals and a vector scan signal of each beam are provided, and the whole blanker is released after the beam is stabilized, and thus high-accuracy and high-speed lithography is performed with a small amount of data. When the total number of shots exceeds a constant value, the pattern data are modified and high-speed lithography is achieved. A semiconductor reversed bias p-n junction technique is preferably used for an individual blanker electrode.


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