The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2014
Filed:
Aug. 17, 2011
Ulrich Moeller, Holzkirchen, DE;
Maik Schaefer, Friedrichshafen-Kluftern, DE;
Ulrich Moeller, Holzkirchen, DE;
Maik Schaefer, Friedrichshafen-Kluftern, DE;
Conti Temic microelectronic GmbH, Nuremberg, DE;
Abstract
The invention relates to a multi-level circuit board for high-frequency applications with at least one first carrier substrate (PCB1) made of a first material suitable for high frequencies and with at least one second carrier substrate (PCB2,3) made of a second material, which second material has higher dielectric losses than the first material. At least one signal line structure (S, C) is provided on the first carrier substrate (PCB1), and at least one ground layer (M) connected to electric ground potential is provided on a side of at least one second carrier substrate (PCB2, PCB3), and electrical vias (V) extending through the carrier substrates (PCB1,2,3) are provided. A capacitance for removing high-frequency power to ground potential is formed through the at least one second carrier substrate (PCB2, PCB3) toward the ground layer (M, M), preferably through two carrier substrates made of the second material toward a metallization surface lying therebetween, in that a metallization surface (C) having a size corresponding to the desired capacitance is formed on that side of the second carrier substrate (PCB2,4) which is opposite the ground layer (M, M) and the metallization surface (C) is connected to the signal line structure (C) by means of a via (V(C-C)).