The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2014

Filed:

Nov. 30, 2009
Applicants:

Jin-ho Seol, Seongnam-si, KR;

Seung-ryoul Maeng, Seongnam-si, KR;

Jin-soo Kim, Seongnam-si, KR;

Jae-geuk Kim, Seongnam-si, KR;

Hyo-taek Shim, Seongnam-si, KR;

Han-mook Park, Seongnam-si, KR;

Inventors:

Jin-Ho Seol, Seongnam-si, KR;

Seung-Ryoul Maeng, Seongnam-si, KR;

Jin-Soo Kim, Seongnam-si, KR;

Jae-Geuk Kim, Seongnam-si, KR;

Hyo-Taek Shim, Seongnam-si, KR;

Han-Mook Park, Seongnam-si, KR;

Assignee:

OCZ Storage Solutions, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/02 (2006.01); G06F 12/12 (2006.01); G06F 12/08 (2006.01);
U.S. Cl.
CPC ...
G06F 12/121 (2013.01); G06F 12/0866 (2013.01); G06F 2212/214 (2013.01); G06F 12/0246 (2013.01);
Abstract

Provided are a method and apparatus for programming a buffer cache in a Solid State Disk (SSD) system. The buffer cache programming apparatus in the SSD system may include a buffer cache unit to store pages, a memory unit including a plurality of memory chips, and a control unit to select at least one of the page as a victim page, based on a delay occurring when a page is stored in at least one target memory chip among the plurality of memory chips.


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