The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 28, 2014
Filed:
May. 09, 2012
Display device and timepiece comprising a wiring board layered on a back surface of a back substrate
Applicants:
Shigeaki Seki, Nagano-ken, JP;
Kenichi Okuhara, Nagano-ken, JP;
Inventors:
Shigeaki Seki, Nagano-ken, JP;
Kenichi Okuhara, Nagano-ken, JP;
Assignee:
Seiko Epson Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1345 (2006.01); G02F 1/13 (2006.01); G04C 19/00 (2006.01); G04C 17/00 (2006.01); G04G 9/00 (2006.01); G02F 1/167 (2006.01); G02F 1/1339 (2006.01); H01R 12/70 (2011.01);
U.S. Cl.
CPC ...
G02F 1/13452 (2013.01); G02F 1/167 (2013.01); G02F 1/1339 (2013.01); H01R 12/7076 (2013.01); G04G 9/0082 (2013.01);
Abstract
A display device that has a display panel having a front substrate, an image forming unit, and a back substrate rendered together in layers, and a wiring board layered on the back surface of the back substrate. A plurality of input/output pins are formed on the front surface of the back substrate, and a plurality of connection pins that are electrically connected to the input/output pins by respective conductor members are formed on the back surface of the wiring board.