The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2014

Filed:

Jul. 15, 2013
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Seon Kwang Jeon, Icheon-si, KR;

Chang Il Kim, Busan, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/02 (2006.01); H01L 25/065 (2006.01); G11C 8/12 (2006.01);
U.S. Cl.
CPC ...
G11C 8/12 (2013.01); H01L 25/0657 (2013.01);
Abstract

A stack package may include a plurality of chips stacked with a plurality of layers; and a chip selection controller configured to provide a reference and chip selection control signal to the plurality of chips. Each chip may comprise: a reference signal controller configured to transmit the reference signal through a first line interconnecting the plurality of chips; a chip selection delay unit configured to control a delay timing point of the chip selection control signal to transmit the control result to each node of a second line interconnecting the plurality of chips; a delay-time-difference sensing unit configured to calculate a delay time difference between a signal applied to each node of the first and second line to generate chip selection information corresponding to the calculated delay time difference; and a memory unit configured to store the chip selection information.


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