The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 28, 2014

Filed:

Oct. 18, 2012
Applicants:

Haruka Shimizu, Kodaira, JP;

Natsuki Yokoyama, Mitaka, JP;

Inventors:

Haruka Shimizu, Kodaira, JP;

Natsuki Yokoyama, Mitaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/161 (2006.01); H01L 29/868 (2006.01); H01L 27/06 (2006.01); H01L 29/808 (2006.01); H01L 21/82 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/8083 (2013.01); H01L 29/868 (2013.01); H01L 27/0629 (2013.01); H01L 21/8213 (2013.01); H01L 29/66909 (2013.01);
Abstract

A normally-off type silicon carbide junction FET has a problem that the gate thereof is not easy to use due to inferiority in the characteristics of it. This problem occurs because in order to achieve normally-off, the gate voltage should be off at 0V and at the same time, the ON-state gate voltage should be suppressed to about 2.5V to prevent the passage of an electric current through a pn junction between gate and source. Accordingly, a range from the threshold voltage to the ON-state gate voltage is only from about 1 V to 2V and it is difficult to control the gate voltage. Provided in the present invention is an electronic circuit device obtained by coupling, to a gate of a normally-off type silicon carbide junction FET, an element having a capacitance equal to or a little smaller than the gate capacitance of the junction FET.


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