The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2014
Filed:
Mar. 27, 2012
Applicants:
Rikizo Nakano, Kawasaki, JP;
Osamu Ishibashi, Kawasaki, JP;
Sadao Miyazaki, Kawasaki, JP;
Inventors:
Assignee:
Fujitsu Limited, Kawasaki, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 13/00 (2006.01); H03K 19/003 (2006.01); H03K 19/094 (2006.01); G11C 29/50 (2006.01); G11C 29/02 (2006.01); G11C 29/04 (2006.01); G01R 31/3187 (2006.01); G11C 29/12 (2006.01); G11C 29/08 (2006.01); G11C 29/14 (2006.01); H04L 25/02 (2006.01);
U.S. Cl.
CPC ...
G11C 29/50012 (2013.01); G11C 29/02 (2013.01); G11C 29/04 (2013.01); G01R 31/3187 (2013.01); G11C 29/12 (2013.01); G11C 29/00 (2013.01); G11C 29/08 (2013.01); G11C 29/14 (2013.01); H04L 25/0278 (2013.01); G11C 29/1201 (2013.01);
Abstract
A semiconductor memory device is disclosed that includes an ODT circuit configured to be connected to a bus which transmits a data signal or a data strobe signal between a memory block and an input-output terminal; a first switch configured to be inserted into the bus between the memory block and the ODT circuit; a mode controller configured to switch off the first switch during a test of the memory block; and an oscillator configured to be connected to the ODT circuit, wherein a test signal is supplied to the ODT circuit from the oscillator during the test of the memory block.