The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2014

Filed:

Feb. 06, 2012
Applicants:

Suresh Natarajan Rajan, San Jose, CA (US);

Keith R. Schakel, San Jose, CA (US);

Michael John Sebastian Smith, Palo Alto, CA (US);

David T. Wang, San Jose, CA (US);

Frederick Daniel Weber, San Jose, CA (US);

Inventors:

Suresh Natarajan Rajan, San Jose, CA (US);

Keith R. Schakel, San Jose, CA (US);

Michael John Sebastian Smith, Palo Alto, CA (US);

David T. Wang, San Jose, CA (US);

Frederick Daniel Weber, San Jose, CA (US);

Assignee:

Google Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G11C 7/10 (2006.01); G11C 11/4063 (2006.01);
U.S. Cl.
CPC ...
G11C 7/10 (2013.01); G11C 11/4063 (2013.01);
Abstract

A method includes presenting multiple memory circuits to a system as a virtual memory circuit having at least one characteristic that is different from a corresponding characteristic of one of the physical memory circuits; receiving, at an interface circuit, a first command issued from the system to the virtual memory circuit; and in response to receiving the first command, 1) directing a copy of the first command to a first physical memory circuit of the multiple physical memory circuits, and 2) performing a power-saving operation on at least one other physical memory circuit of the multiple physical memory circuits.


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