The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2014
Filed:
May. 24, 2011
Brian E. Bakke, Rochester, MN (US);
Brian L. Bowles, Rochester, MN (US);
Michael J. Carnevale, Rochester, MN (US);
Robert E. Galbraith, Ii, Rochester, MN (US);
Adrian C. Gerhard, Rochester, MN (US);
Murali N. Iyer, Rochester, MN (US);
Daniel F. Moertl, Rochester, MN (US);
Mark J. Moran, Minneapolis, MN (US);
Gowrisankar Radhakrishnan, Rochester, MN (US);
Rick A. Weckwerth, Oronoco, MN (US);
Donald J. Ziebarth, Rochester, MN (US);
Brian E. Bakke, Rochester, MN (US);
Brian L. Bowles, Rochester, MN (US);
Michael J. Carnevale, Rochester, MN (US);
Robert E. Galbraith, II, Rochester, MN (US);
Adrian C. Gerhard, Rochester, MN (US);
Murali N. Iyer, Rochester, MN (US);
Daniel F. Moertl, Rochester, MN (US);
Mark J. Moran, Minneapolis, MN (US);
Gowrisankar Radhakrishnan, Rochester, MN (US);
Rick A. Weckwerth, Oronoco, MN (US);
Donald J. Ziebarth, Rochester, MN (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method and controller for implementing storage adapter performance optimization with cache data and cache directory mirroring between dual adapters minimizing firmware operations, and a design structure on which the subject controller circuit resides are provided. One of the first controller or the second controller operates in a first initiator mode includes firmware to set up an initiator write operation building a data frame for transferring data and a respective cache line (CL) for each page index to the other controller operating in a second target mode. Respective initiator hardware engines transfers data, reading CLs from an initiator control store, and writing updated CLs to an initiator data store, and simultaneously sends data and updated CLs to the other controller. Respective target hardware engines write data and updated CLs to the target data store, eliminating firmware operations of the controller operating in the second target mode.