The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2014

Filed:

Mar. 31, 2010
Applicants:

Marek Miskowicz, Cracow, PL;

Dariusz Koscielnik, Cracow, PL;

Inventors:

Marek Miskowicz, Cracow, PL;

Dariusz Koscielnik, Cracow, PL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/14 (2006.01); G06F 13/38 (2006.01);
U.S. Cl.
CPC ...
G06F 13/385 (2013.01);
Abstract

A conversion module contains an asynchronous analog-to-digital converter (AADC) with the output signal generated at irregular time intervals, whose output is connected to the input of the buffer memory module (BUF), and the output of the buffer memory module (BUF) is connected through the internal bus (BUS) simultaneously to the source address module (SADR), to the configuration registers module (REG), to the control module of the interface (CM), which the reference generator (RG) is connected to, and to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and moreover the control inputs/outputs () of the control module (CM) are connected respectively to the asynchronous analog-to-digital converter (AADC), to the buffer memory module (BUF), to the source address module (SADR), to the configuration registers module (REG), to the destination address module (DADR), to the selection register module (SELREG), to the transmitter/receiver module (SDM), and to the clock control module (SCM), and on the other hand, the transmitter/receiver module (SDM) output is connected through the controller (SDD) to the data line (SDA) of the I2C bus whose clock line (SCL) is connected through the other controller (SCD) to the clock control module (SCD) output, and what is more the write control output () of the asynchronous analog-to-digital converter (AADC) is connected to the write control input () of the buffer memory module (BUF).


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