The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2014
Filed:
Oct. 23, 2009
Nabeel Shirazi, Saratoga, CA (US);
L. James Hwang, Portola Valley, CA (US);
Chi Bun Chan, San Jose, CA (US);
Hem C. Neema, Sunnyvale, CA (US);
Kumar Deepak, San Jose, CA (US);
Nabeel Shirazi, Saratoga, CA (US);
L. James Hwang, Portola Valley, CA (US);
Chi Bun Chan, San Jose, CA (US);
Hem C. Neema, Sunnyvale, CA (US);
Kumar Deepak, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A method and apparatus for verifying and debugging a circuit design module of a high level programming system is disclosed herein. A circuit design created in a high level programming environment must undergo a number of transformations as it is compiled into a form that can be realized in hardware. At each transformative step, the behavior of the circuit must be verified with a simulation model and debugged if the transformation has changed the behavior of the circuit. The claimed invention presents a novel approach for verifying and debugging between different simulation models and achieves an advance in the art by utilizing the modularized structure of a high-level circuit design to systematically identify simulation mismatches among different simulation models and determine which portions of the circuit design are responsible for the discrepancy.