The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2014

Filed:

Nov. 21, 2013
Applicant:

True Circuits, Inc., Los Altos, CA (US);

Inventors:

John George Maneatis, Los Altos, CA (US);

Jaeha Kim, Mountain View, CA (US);

Daniel Karl Hartman, Littleton, MA (US);

Assignee:

True Circuits, Inc., Los Altos, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01); H03L 7/07 (2006.01); H03L 7/089 (2006.01); H03L 7/08 (2006.01); H03L 7/081 (2006.01);
U.S. Cl.
CPC ...
H03L 7/089 (2013.01); H03L 7/07 (2013.01); H03L 7/0895 (2013.01); H03L 7/08 (2013.01); H03L 7/0896 (2013.01); H03L 7/0812 (2013.01);
Abstract

A delay-locked loop, including a phase detector configured to receive two signals, one of the signals being delayed relative to the other of the signals, the phase detector having an UP output and a DOWN output. The delay-locked loop also includes a charge pump system operatively coupled with the phase detector, the charge pump system including (1) a charge pump configured to be responsive to assertion of actuating signals from the UP output and the DOWN output so as to control pumping of charge from the charge pump system, such pumped charge being usable to control a delay line carrying one of the two signals, so as to control relative delay occurring between the two signals; and (2) a feedback control loop configured to dynamically adjust at least one bias signal at the charge pump so as to minimize net charge pumped from the charge pump system during simultaneous assertion of actuating signals from the UP output and the DOWN output.


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