The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2014
Filed:
Jun. 27, 2012
Ming-hsueh Wu, Kaohsiung, TW;
Kun-lun Luo, Hsinchu, TW;
Chen-an Chen, Kaohsiung, TW;
Yee-wen Chen, Hsinchu, TW;
Ming-Hsueh Wu, Kaohsiung, TW;
Kun-Lun Luo, Hsinchu, TW;
Chen-An Chen, Kaohsiung, TW;
Yee-Wen Chen, Hsinchu, TW;
Industrial Technology Research Institute, Hsinchu, TW;
Abstract
A repairable multi-layer memory chip stack wherein each of the memory chips of the chip stack includes a control unit, a decoding unit, a memory array module and a redundant repair unit comprising at least one redundant repair element. The decoding unit receives a memory address from an address bus, and correspondingly outputs a decoded address. The memory array module determines whether to allow a data bus to access the data of the memory array module corresponding to a decoded address in accordance with an activation signal of the control unit. The redundant repair element includes a valid field, a chip ID field, a faulty address field and a redundant memory. When the valid field is valid, the value of the chip ID field matches the ID code, and the value of the faulty address field matches the decoded address, the redundant memory is coupled to the data bus.