The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2014
Filed:
Jul. 29, 2010
Applicants:
Hideki Ogawa, Suwa-gun, JP;
Yoshiro Iwasa, Matsumoto, JP;
Inventors:
Hideki Ogawa, Suwa-gun, JP;
Yoshiro Iwasa, Matsumoto, JP;
Assignee:
Seiko Epson Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 1/60 (2006.01); G11C 5/02 (2006.01); H01L 23/00 (2006.01); G09G 5/39 (2006.01); G09G 5/393 (2006.01); G09G 5/395 (2006.01);
U.S. Cl.
CPC ...
G09G 5/39 (2013.01); G09G 5/393 (2013.01); H01L 2924/01006 (2013.01); G09G 5/395 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01061 (2013.01); G11C 5/02 (2013.01); H01L 24/49 (2013.01); H01L 2924/01055 (2013.01); H01L 2924/01005 (2013.01); H01L 2924/01056 (2013.01); H01L 2924/01033 (2013.01); G09G 2360/18 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49171 (2013.01); H01L 2924/01082 (2013.01); H01L 2224/48145 (2013.01);
Abstract
An integrated circuit device includes: a first pad to an ith pad connected to a first memory pad to an ith memory pad of a memory stacked in the integrated circuit device; a jth pad to a kth pad connected to a jth memory pad to a kth (1<i<j<k) memory pad of the memory; and at least one pad arranged between the ith pad and the jth pad, wherein the at least one pad is not connected to a memory pad of the memory and serves as a pad for input or output a signal between an external device and the integrated circuit device.