The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2014

Filed:

May. 18, 2010
Applicants:

Shuji Nishi, Osaka, JP;

Yuhichiroh Murakami, Osaka, JP;

Shige Furuta, Osaka, JP;

Yasushi Sasaki, Osaka, JP;

Seijirou Gyouten, Osaka, JP;

Inventors:

Shuji Nishi, Osaka, JP;

Yuhichiroh Murakami, Osaka, JP;

Shige Furuta, Osaka, JP;

Yasushi Sasaki, Osaka, JP;

Seijirou Gyouten, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); H01L 27/108 (2006.01); G11C 11/406 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 27/108 (2013.01); G09G 3/3648 (2013.01); G11C 2211/4067 (2013.01); G09G 3/3659 (2013.01); G09G 2330/021 (2013.01); G09G 3/3618 (2013.01); G09G 2300/0823 (2013.01); G09G 3/3614 (2013.01); G09G 2300/0852 (2013.01); G11C 11/406 (2013.01); H01L 27/12 (2013.01);
Abstract

A transistor (N) has a gate terminal connected to a word line (Xi()) and a first conduction terminal connected to a bit line (Yj). A transistor (N) has a gate terminal connected to the word line (Xi()) and a first conduction terminal connected to a node (PIX). A transistor (N) has a gate terminal connected to a node (MRY) and a first conduction terminal connected to the word line (Xi()). A transistor (N) has a gate terminal connected to the word line (Xi()), a first conduction terminal connected to a second conduction terminal of the transistor (N), and a second conduction terminal connected to the node (PIX). Capacitors (Ca), (Cb), (Cap) are formed between the node (PIX) and a reference electric potential wire (RL), between the node (MRY) and the reference electric potential wire (RL), and between the first conduction terminal of the transistor (N) and the node (MRY), respectively.


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