The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2014

Filed:

Nov. 22, 2010
Applicants:

Yoshitaka Sasago, Tachikawa, JP;

Masaharu Kinoshita, Tsukuba, JP;

Takahiro Morikawa, Tsukuba, JP;

Akio Shima, Hino, JP;

Takashi Kobayashi, Higashimurayama, JP;

Inventors:

Yoshitaka Sasago, Tachikawa, JP;

Masaharu Kinoshita, Tsukuba, JP;

Takahiro Morikawa, Tsukuba, JP;

Akio Shima, Hino, JP;

Takashi Kobayashi, Higashimurayama, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 47/00 (2006.01); H01L 45/00 (2006.01); H01L 29/792 (2006.01); H01L 27/24 (2006.01); H01L 29/66 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 45/06 (2013.01); H01L 45/1683 (2013.01); H01L 29/7926 (2013.01); H01L 45/144 (2013.01); H01L 45/1616 (2013.01); H01L 27/2454 (2013.01); H01L 27/249 (2013.01); H01L 27/1157 (2013.01); H01L 45/1608 (2013.01); H01L 27/11582 (2013.01); H01L 29/66833 (2013.01);
Abstract

A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.


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