The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2014
Filed:
Sep. 02, 2010
Yoshito Kitagawa, Osaka, JP;
Naoyuki Tani, Osaka, JP;
Toshiyuki Asahi, Osaka, JP;
Panasonic Corporation, Osaka, JP;
Abstract
A multi-layer printed-wiring-board is used in densely packaging electronic components such as semiconductors having improved function, and a production method therefor, and more specifically it achieves a multi-layer printed-wiring-board having excellent copper-foil-peel-strength and high connection-reliability in which occurrence of structural defects such as delamination (interlayer peeling) is prevented, and a production method therefor. Because of thinning of the printed-wiring-board or diversification of insulating layers constituting the printed-wiring-board, peeling such as delamination may occur between the insulating layers or in an interface between the insulating layer and the plated conductor. By providing pores in substantially the same plane as wiring patterns in the printed-wiring-board including insulating layers, wiring pattern layers made of copper foil alternately laminated on the insulating layers, and pores provided between the wiring patterns, a printed-wiring-board having high connection reliability free from delamination or cracks during heating or in heat cycle conditions.