The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2014

Filed:

Aug. 31, 2012
Applicant:

Duk Eui Lee, Seoul, KR;

Inventor:

Duk Eui Lee, Seoul, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/764 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11524 (2013.01); H01L 21/764 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes forming first and second gate lines over a semiconductor substrate, wherein each second gate line has a greater width than each of the first gate lines, forming a first insulating layer surrounding the top and side walls of the first and the second gate lines so that first air gaps are formed between the first and second gate lines and between the first gate lines, forming a first reaction region in the first insulating layer by diffusing an etchant to a depth less than a target depth from a surface of the first insulating layer, removing the first reaction region, forming second reaction regions in the first insulating layer by diffusing the etchant to the target depth from the surface of the first insulating layer, and removing the second reaction regions exposing a portion of each first and second gate lines.


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