The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2014
Filed:
Jun. 18, 2012
Pradip Bose, Yorktown Heights, NY (US);
Alper Buyuktosunoglu, White Plains, NY (US);
John A. Darringer, Mahopac, NY (US);
Moinuddin K. Qureshi, White Plains, NY (US);
Jeonghee Shin, Millwood, NY (US);
Pradip Bose, Yorktown Heights, NY (US);
Alper Buyuktosunoglu, White Plains, NY (US);
John A. Darringer, Mahopac, NY (US);
Moinuddin K. Qureshi, White Plains, NY (US);
Jeonghee Shin, Millwood, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A dynamic system coupled with 'pre-Silicon' design methodologies and 'post-Silicon' current optimizing programming methodologies to improve and optimize current delivery into a chip, which is limited by the physical properties of the connections (e.g., Controlled Collapse Chip Connection or C4s). The mechanism consists of measuring or estimating power consumption at a certain granularity within a chip, converting the power information into C4 current information using a method, and triggering throttling mechanisms (including token based throttling) where applicable to limit the current delivery per C4 beyond pre-established limits or periods. Design aids are used to allocate C4s throughout the chip based on the current delivery requirements. The system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3D chip stack.