The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 14, 2014
Filed:
Dec. 02, 2011
Alexander J. Branover, Chestnut Hill, MA (US);
Madhu Saravana Sibi Govindan, Austin, TX (US);
Guhan Krishnan, Chelmsford, MA (US);
Hemant R. Mohapatra, Cambridge, GB;
Andrew W. Lueck, Austin, TX (US);
Alexander J. Branover, Chestnut Hill, MA (US);
Madhu Saravana Sibi Govindan, Austin, TX (US);
Guhan Krishnan, Chelmsford, MA (US);
Hemant R. Mohapatra, Cambridge, GB;
Andrew W. Lueck, Austin, TX (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A system and method for efficient management of operating modes within an IC for optimal power and performance targets. On a same die, an SOC includes one or more processing units and a input/output (I/O) controller (IOC). The multiple interfaces within the IOC manage packets and messages according multiple different protocols. The IOC maintains an activity level for each one of the multiple interfaces. This activity level may be based at least on a respective number of transactions executed by a corresponding one of the multiple interfaces. The IOC determines a power estimate for itself based on at least the activity levels. In response to detecting a difference between the power estimate and an assigned I/O power limit for the IOC, a power manager adjusts at least respective power limits for the one or more processing units based on at least the difference.