The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2014

Filed:

Dec. 21, 2012
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Tahoma Toelkes, San Jose, CA (US);

Nir Jacob Wakrat, Los Altos, CA (US);

Kenneth L Herman, San Jose, CA (US);

Barry Corlett, Brisbane, CA (US);

Vadim Khmelnitsky, Foster City, CA (US);

Anthony Fai, Palo Alto, CA (US);

Daniel Jeffrey Post, Campbell, CA (US);

Hsiao Thio, San Jose, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 12/02 (2006.01); G06F 12/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0246 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/7208 (2013.01); G06F 12/0607 (2013.01);
Abstract

The disclosed architecture uses address mapping to map a block address on a host interface to an internal block address of a non-volatile memory (NVM) device. The block address is mapped to an internal chip select for selecting a Concurrently Addressable Unit (CAU) identified by the block address. The disclosed architecture supports generic NVM commands for read, write, erase and get status operations. The architecture also supports an extended command set for supporting read and write operations that leverage a multiple CAU architecture.


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