The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2014

Filed:

Sep. 30, 2009
Applicants:

Xiaoqian Zhang, Shanghai, CN;

Shubing Zhai, Shanghai, CN;

Yanbo Wang, Shanghai, CN;

Inventors:

Xiaoqian Zhang, Shanghai, CN;

Shubing Zhai, Shanghai, CN;

Yanbo Wang, Shanghai, CN;

Assignee:

Synaptics Incorporated, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03D 3/24 (2006.01); H03L 7/197 (2006.01); H04N 21/43 (2011.01); H03L 7/193 (2006.01); H04N 21/41 (2011.01); H04J 3/06 (2006.01); G09G 5/00 (2006.01);
U.S. Cl.
CPC ...
H04J 3/062 (2013.01); H03L 7/1978 (2013.01); H04N 21/4307 (2013.01); H03L 7/193 (2013.01); H04N 21/4122 (2013.01); G09G 5/008 (2013.01);
Abstract

The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-Delta Modulator (SDM), and a clock data calibrator to fully recover the original source stream clock data. The fractional-N PLL provides flexible source stream clock recovery. When there is a frequency deviation between the original clock and the regenerated clock, the clock data calibrator control circuit adjusts the clock data, preventing any stream data buffer overflow or underflow problems. The disclosed techniques are compatible with the sink devices based on the standards of DisplayPort and HDMI.


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