Receiving device and demodulation device

Abstract

To adequately perform sampling, a receiving device that solves problems that involve an increase in circuit area and an increase in cost, is provided. A/D convertersamples a coherent signal that is an analog signal in synchronization with a sampling clock signal so as to convert the analog signal into a digital signal. DSPdemodulates the digital signal converted by A/D converterand computes a phase of the sampling clock signal in which an error rate of the digital signal is the minimum based on the demodulated digital signal. Sampling clock extraction circuitextracts a clock signal having a symbol rate of the coherent signal therefrom. Phase adjustment circuitadjusts the phase of the clock signal extracted by sampling clock extraction circuitto the phase computed by DSPand generates a clock signal having the adjusted phase as the sampling clock signal.