The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2014

Filed:

May. 07, 2010
Applicants:

Satoshi Azuma, Tokyo, JP;

Takeshi Oi, Tokyo, JP;

Akihiko Iwata, Tokyo, JP;

Inventors:

Satoshi Azuma, Tokyo, JP;

Takeshi Oi, Tokyo, JP;

Akihiko Iwata, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02M 7/48 (2006.01); H02M 7/49 (2007.01);
U.S. Cl.
CPC ...
H02M 7/49 (2013.01); Y02B 70/1483 (2013.01);
Abstract

A power converting apparatus includes a main inverter having a high-voltage DC power supply that operates at a low frequency employing SiC MOSFETs having a high withstand voltage exceeding 600 V and a sub-inverter having a low-voltage capacitor that operates through high-frequency PWM employing Si MOSFETs having a low withstand voltage. With AC sides of the main inverter and the sub-inverter connected in series, the power converting apparatus outputs AC power having a prescribed voltage waveform by adding voltages individually generated by the main inverter and the sub-inverter. Specifically, the SiC MOSFETs are used only in the main inverter of which devices are required to have a high withstand voltage and the Si MOSFETs are used in the sub-inverter of which devices may have a relatively low withstand voltage, whereby conduction loss is reduced with an inexpensive circuit configuration.


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