The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 14, 2014

Filed:

Mar. 22, 2013
Applicant:

Nujira Limited, Cambourne, GB;

Inventor:

Gerard Wimpenny, Cambourne, GB;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 3/26 (2006.01); H03F 1/32 (2006.01); H03F 1/02 (2006.01);
U.S. Cl.
CPC ...
H03F 3/26 (2013.01); H03F 3/265 (2013.01); H03F 2203/45528 (2013.01); H03F 1/3205 (2013.01); H06F 1/308 (2013.01); H03F 1/0272 (2013.01); H06F 3/45475 (2013.01);
Abstract

An amplification stage comprising: a combiner to generate a sum input signal by combining a voltage signal with a DC bias voltage; a subtractor to generate a difference input signal by subtracting the voltage signal from the DC bias voltage; a first transistor for generating a first part of an amplifier output signal from the sum input signal; a second transistor for generating a second part of an amplifier output signal from the difference input signal; a combiner for combining the first and second parts of the amplifier output signal; a sensing circuit arranged to sense a current flowing in each of the first and second transistors; a control circuit arranged to determine the quiescent current of the first and second transistors in dependence on the sensed currents; and an adjustment circuit arranged to adjust the DC bias voltage in order to minimize variation in the quiescent current.


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